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FEATURES
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LTC2301/LTC2305 1-/2-Channel, 12-Bit ADCs with I2C Compatible Interface DESCRIPTION
The LTC(R)2301/LTC2305 are low noise, low power, 1-/2channel, 12-bit successive approximation ADCs with an I2C compatible serial interface. These ADCs include an internal reference and a fully differential sample-and-hold circuit to reduce common-mode noise. The LTC2301/LTC2305 operate from an internal clock to achieve a fast 1.3s conversion time. The LTC2301/LTC2305 operate from a single 5V supply and draw just 300A at a throughput rate of 1ksps. The ADC enters nap mode when not converting, reducing the power dissipation. The LTC2301/LTC2305 are available in small 12-pin 4mm x 3mm DFN and 12-pin MSOP packages. The internal 2.5V reference further reduces PCB board space requirements. The low power consumption and small size make the LTC2301/LTC2305 ideal for battery operated and portable applications, while the 2-wire I2C compatible serial interface makes these ADCs a good match for space-constrained systems.
12-Bit I2C ADC Famly
Input Channels Part Number 1 LTC2301 2 LTC2305 8 LTC2309
12-Bit Resolution Low Power: 1.5mW at 1ksps, 35W Sleep Mode 14ksps Throughput Rate Internal Reference Low Noise: SNR = 73.5dB Guaranteed No Missing Codes Single 5V Supply 2-wire I2C Compatible Serial Interface with 9 Addresses Plus One Global for Synchronization Fast Conversion Time: 1.3s 1-Channel (LTC2301) and 2-Channel (LTC2305) Versions Unipolar or Bipolar Input Ranges (Software Selectable) Internal Conversion Clock Guaranteed Operation from -40C to 125C (MSOP Package) 12-Pin 4mm x 3mm DFN and 12-Pin MSOP Packages
APPLICATIONS
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Industrial Process Control Motor Control Accelerometer Measurements Battery Operated Instruments Isolated and/or Remote Data Acquisition Power Supply Monitoring
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
BLOCK DIAGRAM
5V 10F LTC2301 LTC2305 CH0(IN+) ANALOG INPUT 0V TO 4.096V UNIPOLAR CH1(IN+) 2.048V BIPOLAR ANALOG INPUT MUX + - VDD 0.1F AD1 AD0 SCL SDA VREF 2.2F
Integral Nonlinearity vs Output Code (LTC2305)
1.00 0.75 0.50 INL (LSB) REFCOMP 10F 0.25 0.00 -0.25 -0.50 -0.75 -1.00 0 1024 2048 3072 OUTPUT CODE 4096
23015 TA01b
12-BIT SAR ADC
I2C PORT
INTERNAL 2.5V REF PIN NAMES IN PARENTHESES REFER TO LTC2301 GND
23015 TA01a
0.1F
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LTC2301/LTC2305 ABSOLUTE MAXIMUM RATINGS
(Notes 1,2)
Supply Voltage (VDD) ................................ -0.3V to 6.0V Analog Input Voltage CH0(IN+), CH1(IN-), REF, REFCOMP .....................(GND - 0.3V) to (VDD + 0.3V) Digital Input Voltage..........(GND - 0.3V) to (VDD + 0.3V) Digital Output Voltage .......(GND - 0.3V) to (VDD + 0.3V)
Power Dissipation ...............................................500mW Operating Temperature Range LTC2301C/LTC2305C ............................... 0C to 70C LTC2301I/LTC2305I.............................. -40C to 85C LTC2301H/LTC2305H (Note 13) ......... -40C to 125C Storage Temperature Range................... -65C to 150C
PIN CONFIGURATION
LTC2305
GND SDA SCL GND CH0 CH1 1 2 3 4 5 6 13 TOP VIEW 12 AD0 11 AD1 10 VDD 9 8 7 GND REFCOMP VREF
LTC2301
GND SDA SCL GND IN
+
TOP VIEW 1 2 3 4 5 6 13 12 AD0 11 AD1 10 VDD 9 8 7 GND REFCOMP VREF
IN-
DE PACKAGE 12-LEAD (4mm x 3mm) PLASTIC DFN TJMAX = 150C, JA = 43C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
DE PACKAGE 12-LEAD (4mm x 3mm) PLASTIC DFN TJMAX = 150C, JA = 43C/W EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
LTC2305
GND SDA SCL GND CH0 CH1 1 2 3 4 5 6
TOP VIEW 12 11 10 9 8 7 AD0 AD1 VDD GND REFCOMP VREF
LTC2301
GND SDA SCL GND IN+ IN- 1 2 3 4 5 6
TOP VIEW 12 11 10 9 8 7 AD0 AD1 VDD GND REFCOMP VREF
MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 150C, JA = 130C/W
MS PACKAGE 12-LEAD PLASTIC MSOP TJMAX = 150C, JA = 130C/W
ORDER INFORMATION
LEAD FREE FINISH LTC2301CDE#PBF LTC2301IDE#PBF LTC2305CDE#PBF LTC2305IDE#PBF LTC2301CMS#PBF LTC2301IMS#PBF LTC2301HMS#PBF LTC2305CMS#PBF TAPE AND REEL LTC2301CDE#TRPBF LTC2301IDE#TRPBF LTC2305CDE#TRPBF LTC2305IDE#TRPBF LTC2301CMS#TRPBF LTC2301IMS#TRPBF LTC2301HMS#TRPBF LTC2305CMS#TRPBF PART MARKING* 2301 2301 2305 2305 2301 2301 2301 2305 PACKAGE DESCRIPTION 12-Lead (3mm x 4mm) Plastic DFN 12-Lead (3mm x 4mm) Plastic DFN 12-Lead (3mm x 4mm) Plastic DFN 12-Lead (3mm x 4mm) Plastic DFN 12-Lead Plastic MSOP 12-Lead Plastic MSOP 12-Lead Plastic MSOP 12-Lead Plastic MSOP TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C -40C to 125C 0C to 70C
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LTC2301/LTC2305 ORDER INFORMATION
LEAD FREE FINISH LTC2305IMS#PBF LTC2305HMS#PBF TAPE AND REEL LTC2305IMS#TRPBF LTC2305HMS#TRPBF PART MARKING* 2305 2305 PACKAGE DESCRIPTION 12-Lead Plastic MSOP 12-Lead Plastic MSOP TEMPERATURE RANGE -40C to 85C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER AND MULTIPLEXER CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Bipolar Zero Error Bipolar Zero Error Drift Unipolar Zero Error Unipolar Zero Error Drift Unipolar Zero Error Match (LTC2305) Bipolar Full-Scale Error Bipolar Full-Scale Error Drift Unipolar Full-Scale Error Unipolar Full-Scale Error Drift Unipolar Full-Scale Error Match (LTC2305) External Reference (Note 7) REFCOMP = 4.096V (Note 7) External Reference External Reference (Note 7) REFCOMP = 4.096V (Note 7) External Reference
l l l l
CONDITIONS
l
MIN 12
l l l l
TYP 0.4 0.3 0.5 0.002 0.7 0.002 0.1 1 0.9 0.05 0.5 0.7 0.05 0.1
MAX 1 1 8 6 1 10 9 10 6 2
UNITS Bits LSB LSB LSB LSB/C LSB LSB/C LSB LSB LSB LSB/C LSB LSB LSB/C LSB
(Note 5) (Note 6) (Note 6)
ANALOG INPUT
SYMBOL VIN+ VIN- VIN+ - VIN- IIN CIN CMRR PARAMETER
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS (Note 8) Unipolar (Note 8) Bipolar (Note 8) VIN = VIN+ - VIN- (Unipolar) VIN = VIN+ - VIN- (Bipolar) Sample Mode Hold Mode
l l l l
MIN -0.05 -0.05 -0.05
TYP
MAX REFCOMP 0.25 * REFCOMP 0.75 * REFCOMP
UNITS V V V V V
Absolute Input Range (CH0, CH1, IN+) Absolute Input Range (CH0, CH1, IN-) Input Differential Voltage Range Analog Input Leakage Current Analog Input Capacitance Input Common Mode Rejection Ratio
0 to REFCOMP REFCOMP/2 1 55 5 70
A pF pF dB
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LTC2301/LTC2305 DYNAMIC ACCURACY
SYMBOL SINAD SNR THD SFDR PARAMETER Signal-to-(Noise + Distortion) Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range Channel-to-Channel Isolation Full Linear Bandwidth -3dB Input Linear Bandwidth Aperture Delay Transient Response Full-Scale Step
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and AIN = -1dBFS. (Notes 4,9)
CONDITIONS fIN = 1kHz fIN = 1kHz fIN = 1kHz fIN = 1kHz, First 5 Harmonics fIN = 1kHz fIN = 1kHz (Note 10)
l l l l
MIN 71 71 79
TYP 73.4 73.5 -91 92 -109 700 25 13 240
MAX
UNITS dB dB
-77
dB dB dB kHz MHz ns ns
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 4)
PARAMETER VREF Output Voltage VREF Output Tempco VREF Output Impedance VREFCOMP Output Voltage VREF Line Regulation CONDITIONS IOUT = 0 IOUT = 0 -0.1mA IOUT 0.1mA IOUT = 0 VDD = 4.75V to 5.25V
l
MIN 2.46
TYP 2.50 25 8 4.096 0.8
MAX 2.54
UNITS V ppm/C k V mV/V
I2C INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 4)
SYMBOL PARAMETER VIH VIL VIHA VILA RINH RINL RINF II VHYS VOL tOF tSP CCAX High Level Input Voltage Low Level Input Voltage High Level Input Voltage for Address Pins A1, A0 Low Level Input Voltage for Address Pins A1, A0 Resistance from A1, A0 to VDD to Set Chip Address Bit to 1 Resistance from A1, A0 to GND to Set Chip Address Bit to 0 Resistance from A1, A0 to GND or VDD to Set Chip Address Bit to Float Digital Input Current Hysteresis of Schmitt Trigger Inputs Low Level Output Voltage (SDA) Output Fall Time VIN(MIN) to VIL(MAX) Input Spike Suppression External Capacitance Load on Chip Address Pins (A1, A0) for Valid Float VIN = VDD (Note 8) I = 3mA Bus Load CB 10pF to 400pF (Note 11) CONDITIONS
l l l l l l l l l l l l l
MIN 2.85
TYP
MAX 1.5
UNITS V V V V k k M
4.75 0.25 10 10 2 -10 0.25 0.4 20 + 0.1CB 250 50 10 10
A V V ns ns pF
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LTC2301/LTC2305 POWER REQUIREMENTS
SYMBOL VDD IDD PARAMETER Supply Voltage Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode 14ksps Sample Rate SLP Bit = 0, Conversion Done SLP Bit = 1, Conversion Done 14ksps Sample Rate SLP Bit = 0, Conversion Done SLP Bit = 1, Conversion Done
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l l l l l l
MIN 4.75
TYP 5 2.3 225 7 11.5 1.125 35
MAX 5.25 3.5 400 15 17.5 2 75
UNITS V mA A A mW mW W
PD
I2C TIMING CHARACTERISTICS
SYMBOL fSCL tHD(SDA) tLOW tHIGH tSU(STA) tHD(DAT) tSU(DAT) tr tf tSU(STO) tBUF PARAMETER SCL Clock Frequency Hold Time (Repeated) Start Condition Low Period of the SCL Pin High Period of the SCL Pin Set-Up Time for a Repeated Start Condition Data Hold Time Data Set-Up Time Rise Time for SDA/SCL Signals Fall Time for SDA/SCL Signals Set-Up Time for Stop Condition Bus Free Time Between a Second Start Condition
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l l l l l l l l l l
MIN 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 1.3
TYP
MAX 400
UNITS kHz s s s s
0.9 300 300
s ns ns ns s s
(Note 11) (Note 11)
ADC TIMING CHARACTERISTICS
SYMBOL fSMPL tCONV tACQ tREFWAKE PARAMETER Throughput Rate (Successive Reads) Conversion Time Acquisition Time REFCOMP Wakeup Time (Note 12)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l
MIN
TYP 1.3 200
MAX 14 1.6 240
UNITS ksps s ns ms
(Note 8) CREFCOMP = 10F, CREF = 2.2F
l
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LTC2301/LTC2305 ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. These products can handle input currents greater than 100mA below ground or above VDD without latchup. Note 4: VDD = 5V, fSMPL = 14kHz, internal reference unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Bipolar zero error is the offset voltage measured from -0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Unipolar zero error is the offset voltage measured from 0.5LSB when the output code flickers between 0000 0000 0000 and 0000 0000 0001. Note 7: Full-scale bipolar error is the worst-case of -FS or FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Unipolar full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. Note 8: Guaranteed by design, not subject to test. Note 9: All specifications in dB are referred to a full-scale 2.048V input with a 2.5V reference voltage. Note 10: Full linear bandwidth is defined as the full-scale input frequency at which the SINAD degrades to 60dB or 10 bits of accuracy. Note 11: CB = capacitance of one bus line in pF (10pF CB 400pF) Note 12: REFCOMP wakeup time is the time required for the REFCOMP pin to settle within 0.5LSB at 12-bit resolution of its final value after waking up from sleep mode. Note 13: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105C.
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LTC2301/LTC2305 TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2301) TA = 25C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted. Integral Nonlinearity vs Output Code
1.00 0.75 0.50 DNL (LSB) INL (LSB) 0.25 0.00 1.00 0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 0 1024 2048 3072 OUTPUT CODE 4096
23015 G01
Differential Nonlinearity vs Output Code
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
1kHz Sine Wave 8192 Point FFT Plot
SNR = 73.2 dB SINAD = 73.1 dB THD = -80dB
-0.25 -0.50 -0.75 -1.00
-1.00
0
1024
2048 3072 OUTPUT CODE
4096
23015 G02
MAGNITUDE (dB)
0
1
2
3 4 5 FREQUENCY (kHz)
6
7
23015 G03
Supply Current vs Sampling Frequency
2.5 1.5
Offset Error vs Temperature
4
Full-Scale Error vs Temperature
UNIPOLAR FULL-SCALE ERROR (LSB)
2.0 SUPPLY CURRENT (mA) OFFSET ERROR (LSB)
1.0
2 BIPOLAR 0
1.5
0.5 BIPOLAR
1.0
0.0
-2
0.5
-0.5
UNIPOLAR
-4
0 0.1
1 10 SAMPLING FREQUENCY (ksps)
100
23015 G04
-1.0 -50
-25
0 50 25 75 TEMPERATURE (C)
100
125
-6 -50
-25
0 50 25 75 TEMPERATURE (C)
100
125
23015 G05
23015 G06
Supply Current vs Temperature
2.4 10
Sleep Current vs Temperature
1000 900 LEAKAGE CURRENT (nA) -25 25 75 0 50 TEMPERATURE (C) 125
Analog Input Leakage Current vs Temperature
SUPPLY CURRENT (mA)
SLEEP CURRENT (A)
2.2
8
800 700 600 500 400 300 200 100
6
1.8
4
1.6
2
1.4 -50
-25
25 75 0 50 TEMPERATURE (C)
100
125
0 -50
100
0 -50
-25
25 75 0 50 TEMPERATURE (C)
100
125
23015 G07
23015 G08
23015 G09
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LTC2301/LTC2305 TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2305) TA = 25C, VDD = 5V, fSMPL = 14ksps, unless otherwise noted. Integral Nonlinearity vs Output Code
1.00 0.75 0.50 DNL (LSB) INL (LSB) 0.25 0.00 1.00 0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 0 1024 2048 3072 OUTPUT CODE 4096
23015 G10
Differential Nonlinearity vs Output Code
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
1kHz Sine Wave 8192 Point FFT Plot
SNR = 73.2 dB SINAD = 73.1 dB THD = -80dB
-0.25 -0.50 -0.75 -1.00
0
1024
2048 3072 OUTPUT CODE
4096
23015 G11
MAGNITUDE (dB)
0
1
2
3 4 5 FREQUENCY (kHz)
6
7
23015 G12
Supply Current vs Sampling Frequency
2.5 1.0
Offset Error vs Temperature
4
Full-Scale Error vs Temperature
FULL-SCALE ERROR (LSB)
2.0 SUPPLY CURRENT (mA) OFFSET ERROR (LSB) 0.5
BIPOLAR
2 BIPOLAR 0 UNIPOLAR -2
1.5
1.0
0.0
UNIPOLAR
0.5
-4
0 0.1
1 10 SAMPLING FREQUENCY (ksps)
100
23015 G13
-0.5 -50
-25
0 50 25 75 TEMPERATURE (C)
100
125
-6 -50
-25
0 50 25 75 TEMPERATURE (C)
100
125
23015 G14
23015 G15
Supply Current vs Temperature
2.4 10
Sleep Current vs Temperature
1000 900 LEAKAGE CURRENT (nA)
Analog Input Leakage Current vs Temperature
SUPPLY CURRENT (mA)
SLEEP CURRENT (A)
2.2
8
800 700 600 500 400 300 200 100 CH(ON) CH(OFF)
6
1.8
4
1.6
2
1.4 -50
-25
25 75 0 50 TEMPERATURE (C)
100
125
0 -50
-25
25 75 0 50 TEMPERATURE (C)
100
125
0 -50
-25
25 75 0 50 TEMPERATURE (C)
100
125
23015 G16
23015 G17
23015 G18
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LTC2301/LTC2305 PIN FUNCTIONS
(LTC2301) GND (Pins 1, 4, 9): Ground. All GND pins must be connected to a solid ground plane. SDA (Pin 2): Bidirectional Serial Data Line of the I2C Interface. In transmitter mode (Read), the conversion result is output at the SDA pin, while in receiver mode (Write), the DIN word is input at the SDA pin to configure the ADC. The pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to VDD) during the data output mode. SCL (Pin 3): Serial Clock Pin of the I2C Interface. The LTC2301 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. IN+, IN- (Pins 5, 6): Positive (IN+) and negative (IN-) differential analog inputs. VREF (Pin 7): 2.5V Reference Output. Bypass to GND with a minimum 2.2F tantalum capacitor or low ESR ceramic capacitor. The internal reference may be overdriven by an external 2.5V reference at this pin. REFCOMP (Pin 8): Reference Buffer Output. Bypass to GND with a 10F low ESR ceramic or tantalum and 0.1F ceramic capacitor in parallel. Nominal output voltage is 4.096V. The internal reference buffer driving this pin is disabled by grounding VREF, allowing REFCOMP to be overdriven by an external source (see Figure 5c). VDD (Pin 10): 5V Analog Supply. The range of VDD is 4.75V to 5.25V. Bypass VDD to GND with a 0.1F ceramic and a 10F low ESR ceramic or tantalum capacitor in parallel. AD1 (Pin 11): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, Floating) address control bit for the device I2C address. See Table 2 for address selection. AD0 (Pin 12): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, Floating) address control bit for the device I2C address. See Table 2 for address selection. GND (Pin 13 - DFN Package Only): Exposed Pad Ground. Must be soldered directly to ground plane.
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LTC2301/LTC2305 PIN FUNCTIONS
(LTC2305) GND (Pins 1, 4, 9): Ground. All GND pins must be connected to a solid ground plane. SDA (Pin 2): Bidirectional Serial Data Line of the I2C Interface. In transmitter mode (Read), the conversion result is output at the SDA pin, while in receiver mode (Write), the DIN word is input at the SDA pin to configure the ADC. The pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to VDD) during the data output mode. SCL (Pin 3): Serial Clock Pin of the I2C Interface. The LTC2305 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. CH0-CH1 (Pins 5, 6): Channel 0 and Channel 1 Analog Inputs. CH0 and CH1 can be configured as single-ended or differential input channels. See the Analog Input Multiplexer section. VREF (Pin 7): 2.5V Reference Output. Bypass to GND with a minimum 2.2F tantalum capacitor or low ESR ceramic capacitor. The internal reference may be overdriven by an external 2.5V reference at this pin. REFCOMP (Pin 8): Reference Buffer Output. Bypass to GND with a 10F low ESR ceramic or tantalum and 0.1F ceramic capacitor in parallel. Nominal output voltage is 4.096V. The internal reference buffer driving this pin is disabled by grounding VREF, allowing REFCOMP to be overdriven by an external source (see Figure 5c). VDD (Pin 10): 5V Analog Supply. The range of VDD is 4.75V to 5.25V. Bypass VDD to GND with a 0.1F ceramic and a 10F low ESR ceramic or tantalum capacitor in parallel. AD1 (Pin 11): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, Floating) address control bit for the device I2C address. See Table 2 for address selection. AD0 (Pin 12): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, Floating) address control bit for the device I2C address. See Table 2 for address selection. GND (Pin 13 - DFN Package Only): Exposed Pad Ground. Must be soldered directly to ground plane.
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LTC2301/LTC2305 FUNCTIONAL BLOCK DIAGRAM
VDD LTC2301 LTC2305 CH0(IN+) CH1(IN-) + - 8k AD1 AD0 SCL SDA VREF
ANALOG INPUT MUX
12-BIT SAR ADC
I2C PORT
INTERNAL 2.5V REF GAIN = 1.6384x PIN NAMES IN PARENTHESES REFER TO LTC2301 GND
REFCOMP
23015 BD
TIMING DIAGRAM
Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
SDA tLOW tf SCL tHD(SDA) S tHD(DAT) tHIGH tSU(STA) Sr tSU(STO) P S
23015 TD
tSU(DAT) tr tf
tHD(SDA)
tSP
tr
tBUF
S = START, Sr = REPEATED START, P = STOP
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LTC2301/LTC2305 APPLICATIONS INFORMATION
Overview The LTC2301/LTC2305 are low noise, 1-/2-channel, 12-bit successive approximation register (SAR) A/D converters with an I2C compatible serial interface. The LTC2301/ LTC2305 both include a precision internal reference. The LTC2305 includes a 2-channel analog input multiplexer (MUX) while the LTC2301 includes an input MUX that allows the polarity of the differential input to be selected. These ADCs can operate in either unipolar or bipolar mode. Unipolar mode should be used for single-ended operation with the LTC2305, since single-ended input signals are always referenced to GND. A sleep mode option is also provided to further reduce power during inactive periods. The LTC2301/LTC2305 communicate through a 2-wire I2C compatible serial interface. Conversions are initiated by signaling a stop condition after the part has been successfully addressed for a read/write operation. The device will not acknowledge an external request until the conversion is finished. After a conversion is finished, the device is ready to accept a read/write request. Once the LTC2301/LTC2305 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (SCL). There is no latency in the conversion result. There are 12 bits of output data followed by four trailing zeros. Data is updated on the falling edges of SCL, allowing the user to reliably latch data on the rising edge of SCL. A write operation may follow the read operation by using a repeat start or a stop condition may be given to start a new conversion. By selecting a write operation, these ADCs can be programmed by a 6-bit DIN word. The DIN word configures the MUX and programs various modes of operation. During a conversion, the internal 12-bit capacitive chargeredistribution DAC output is sequenced through a successive approximation algorithm by the SAR starting from the most significant bit (MSB) to the least significant bit (LSB). The sampled input is successively compared with binary weighted charges supplied by the capacitive DAC using a differential comparator. At the end of a conversion, the DAC output balances the analog input. The SAR contents (a 12-bit data word) that represent the sampled analog input are loaded into 12 output latches that allow the data to be shifted out via the I2C interface. Programming the LTC2301 and LTC2305 The software compatible LTC2301/LTC2305/LTC2309 family features a 6-bit DIN word to program various modes of operation. Don't care bits (X) are ignored. The SDA data bits are loaded on the rising edge of SCL during a write operation, with the S/D bit loaded on the first rising edge and the SLP bit on the sixth rising edge (see Figure 7b in the I2C Interface section). The input data word for the LTC2305 is defined as follows: S/D O/S X X UNI SLP
S/D = SINGLE-ENDED/DIFFERENTIAL BIT O/S = ODD/SIGN BIT UNI = UNIPOLAR/BIPOLAR BIT SLP = SLEEP MODE BIT For the LTC2301, the input word is defined as: X O/S X X UNI SLP
Analog Input Multiplexer The analog input MUX is programmed by the S/D and O/S bits of the DIN word for the LTC2305 and the O/S bit of the DIN word for the LTC2301. Table 1 and Table 2 list the MUX configurations for all combinations of the configuration bits. Figure 1a shows several possible MUX configurations and Figure 1b shows how the MUX can be reconfigured from one conversion to the next.
Table 1. Channel Configuration for the LTC2305
S/D 0 0 1 1 O/S 0 1 0 1 CH0 + - + + CH1 - +
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LTC2301/LTC2305 APPLICATIONS INFORMATION
Table 2. Channel Configuration for the LTC2301
O/S 0 1 IN+ + - IN- - +
Driving the Analog Inputs The analog inputs of the LTC2301/LTC2305 are easy to drive. Each of the analog inputs of the LTC2305 (CH0 and CH1) can be used as single-ended input relative to GND or as a differential pair. The analog inputs of the LTC2301 (IN+, IN-) are always configured as a differential pair. Regardless of the MUX configuration, the "+" and "-" inputs are sampled at the same instant. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors during the acquire mode. In conversion mode, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, the ADC inputs can be driven directly. Otherwise, more acquisition time should be allowed for a source with higher impedance. Input Filtering The noise and distortion of the input amplifier and other circuitry must be considered since they will add to the ADC noise and distortion. Therefore, noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. The analog inputs of the LTC2301/LTC2305 can be modeled as a 55pF capacitor (CIN) in series with a 100 resistor (RON) as shown in Figure 2a. CIN gets switched to the selected input once during each conversion. Large filter RC time constants will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle to 12-bit resolution within the acquisition time (tACQ) if DC accuracy is important. When using a filter with a large CFILTER value (e.g. 1F), the inputs do not completely settle and the capacitive input switching currents are averaged into a net DC current(IDC). In this case, the analog input can be modeled by an equivalent resistance (REQ = 1/(fSMPL * CIN)) in series with an ideal voltage source (VREFCOMP/2) as shown in Figure 2b.
1 Differential
2 Single-Ended
+ (-) - (+) {
CH0 CH1
+ +
CH0 CH1
LTC2305
LTC2305
GND (-)
1 Differential
+ (-) - (+) {
CH0 CH1
LTC2301
23015 F01a
Figure 1a. Example MUX Configurations
1st Conversion
2nd Conversion
+ -{
CH0 CH1 LTC2305
- +
{
CH0 CH1 LTC2305 GND (-)
23015 F01b
Figure 1b. Changing the MUX Assignment "On the Fly"
23015f
13
LTC2301/LTC2305 APPLICATIONS INFORMATION
The magnitude of the DC current is then approximately IDC = (VIN - VREFCOMP/2)/REQ, which is roughly proportional to VIN. To prevent large DC drops across the resistor RFILTER, a filter with a small resistor and large capacitor should be chosen. When running at the maximum throughput rate of 14ksps, the input current equals 1.5A at VIN = 4.096V, which amounts to a full-scale error of 0.5LSBs when using a filter resistor (RFILTER) of 333. Applications requiring lower sample rates can tolerate a larger filter resistor for the same amount of full-scale error. Figures 3a and 3b show respective examples of input filtering for single-ended and differential inputs. For the single-ended case in Figure 4a, a 50 source resistor and a 2000pF capacitor to ground on the input will limit the input bandwidth to 1.6MHz. High quality capacitors and resistors should be used in the RC filter since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Dynamic Performance Fast Fourier Transform (FFT) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling
RSOURCE VIN
INPUT CH0, CH1, IN+, IN- CFILTER
ANALOG INPUT RON = 100 LTC2301 LTC2305 CIN = 55pF
23015 F02a
50 CH0, CH1 2000pF LTC2305 REFCOMP 10F 0.1F
23015 F03a
Figure 2a. Analog Input Equivalent Circuit
Figure 3a. Optional RC Input Filtering for Single-Ended Input
RFILTER VIN
IDC
INPUT (CH0, CH1, IN+, IN-) LTC2301 REQ = LTC2305 1/(fSMPL * CIN)
1000pF 50 DIFFERENTIAL ANALOG INPUTS 1000pF 50 1000pF REFCOMP
23015 F02b
CH0, IN+ LTC2301 LTC2305 CH1, IN-
CFILTER
+ -
VREFCOMP/2 10F 0.1F
23015 F03b
Figure 2b. Analog Input Equivalent Circuit for Large Filter Capacitances
Figure 3b. Optional RC Input Filtering for Differential Inputs
23015f
14
LTC2301/LTC2305 APPLICATIONS INFORMATION
frequency. Figure 4 shows a typical SINAD of 73.2dB with a 14kHz sampling rate and a 1kHz input. A SNR of 73.3dB can be achieved with the LTC2301/LTC2305.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 SNR = 73.2dB SINAD = 73.1dB THD = -80dB
MAGNITUDE (dB)
a 0.1F ceramic capacitor for best noise performance. The internal reference buffer can also be overdriven from 1V to VDD with an external reference at REFCOMP as shown in Figure 5c. To do so, VREF must be grounded to disable the reference buffer. This will result in an input range of 0V to VREFCOMP in unipolar mode and 0.5 * VREFCOMP in bipolar mode.
R1 8k
2.5V 2.2F 4.096V 0 1 2 3 4 5 FREQUENCY (kHz) 6 7
23015 F04
VREF
BANDGAP REFERENCE
REFCOMP
+
10F 0.1F GND R3
REFERENCE AMP
R2
Figure 4. 1kHz Sine Wave 8192 Point FFT Plot
Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency(fSMPL/2). THD is expressed as: V2 2 + V3 2 + V4 2 ... + VN 2 THD = 20log V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Internal Reference The LTC2301/LTC2305 have an on-chip, temperature compensated bandgap reference that is factory trimmed to 2.5V (Refer to Figure 5a). It is internally connected to a reference amplifier and is available at VREF (Pin 7). VREF should be bypassed to GND with a 2.2F tantalum capacitor to minimize noise. An 8k resistor is in series with the output so that it can be easily overdriven by an external reference if more accuracy and/or lower drift are required as shown in Figure 5b. The reference amplifier . gains the VREF voltage by 1.638 to 4.096V at REFCOMP To compensate the reference amplifier, bypass REFCOMP with a 10F ceramic or tantalum capacitor in parallel with
0.1F
LTC2301 LTC2305
23015 F05a
Figure 5a. LTC2301/LTC2305 Reference Circuit
5V VIN LT1790A-2.5 VOUT 2.2F
VREF LTC2301 LTC2305 REFCOMP 10F 0.1F GND
23015 F05b
+
Figure 5b. Using the LT1790A-2.5 as an External Reference
5V VIN LT1790A-4.096 VOUT VREF LTC2301 LTC2305
0.1F
+
10F
REFCOMP 0.1F GND
23015 F05c
Figure 5c. Overdriving REFCOMP Using the LT1790A-4.096
23015f
15
LTC2301/LTC2305 APPLICATIONS INFORMATION
Internal Conversion Clock The internal conversion clock is factory trimmed to achieve a typical conversion time (tCONV) of 1.3s and a maximum conversion time of 1.6s over the full operating temperature range. I2C Interface inThe LTC2301/LTC2305 communicate through an terface. The I2C interface is a 2-wire open-drain interface supporting multiple devices and multiple masters on a single bus. The connected devices can only pull the serial data line (SDA) low and can never drive it high. SDA is required to be externally connected to the supply through a pull-up resistor. When the data line is not being driven low, it is high. Data on the I2C bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. Each device on the I2C bus is recognized by a unique address stored in the device and can only operate either as a transmitter or receiver, depending on the function of the device. A device can also be considered as a master or a slave when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit the transfer. Devices addressed by the master are considered slaves. The LTC2301/LTC2305 can only be addressed as slaves. Once addressed, they can receive configuration bits (DIN word) or transmit the last conversion result. The serial clock line (SCL) is always an input to the LTC2301/LTC2305 and the serial data line (SDA) is bidirectional. These devices support the standard mode and the fast mode for data transfer speeds up to 400kbits/s (see Timing Diagram section for definition of the I2C timing). The Start and Stop Conditions Referring to Figure 6, a Start (S) condition is generated by transitioning SDA from high to low while SCL is high. The bus is considered to be busy after the Start condition. When the data transfer is finished, a Stop (P) condition is generated by transitioning SDA from low to high while SCL is high. The bus is free after a Stop condition is generated. Start and Stop conditions are always generated by the master. I2C
SDA SDA
Start Condition
Stop Condition
S SCL
P
23015 F06
SCL
Figure 6. Timing Diagrams of Start and Stop Conditions
When the bus is in use, it stays busy if a Repeated Start (Sr) is generated instead of a Stop condition. The Repeated Start timing is functionally identical to the Start and is used for writing and reading from the device before the initiation of a new conversion. Data Transferring After the Start condition, the I2C bus is busy and data transfer can begin between the master and the addressed slave. Data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ACK) bit. The master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA low or issue a Not Acknowledge (NAK) by leaving the SDA line high impedance (the external pull-up resistor will hold the line high). Change of data only occurs while the SCL line is low. Data Format After a Start condition, the master sends a 7-bit address followed by a read/write (R/W) bit. The R/W bit is 1 for a read request and 0 for a write request. If the 7-bit address matches one of the LTC2301/LTC2305's 9 pinselectable addresses (see Table 2), the ADC is selected. When the ADC is addressed during a conversion, it will not acknowledge R/W requests and will issue a NAK by leaving the SDA line high. If the conversion is complete, the LTC2301/LTC2305 issues an ACK by pulling the SDA line low. The LTC2301/LTC2305 has two registers. The 12-bit wide output register contains the last conversion result. The 6-bit wide input register configures the input MUX and the operating mode of the ADC.
23015f
16
LTC2301/LTC2305 APPLICATIONS INFORMATION
Output Data Format The output register contains the last conversion result. After each conversion is completed, the device automatically enters either nap or sleep mode depending on the setting of the SLP bit (see Nap Mode and Sleep Mode sections). When the LTC2301/LTC2305 is addressed for a read operation, it acknowledges by pulling SDA low and acts as a transmitter. The master/receiver can read up to two bytes from the LTC2301/LTC2305. After a complete read operation of 2 bytes, a Stop condition is needed to initiate a new conversion. The device will NAK subsequent read operations while a conversion is being performed. The data output stream is 16 bits long and is shifted out on the falling edges of SCL (see Figure 7a). The first bit is the MSB and the 12th bit is the LSB of the conversion
1 SCL 2 3 4 5 6 7 8 9
result. The remaining four bits are zero. Figures 13 and 14 are the transfer characteristics for the bipolar and unipolar modes. Data is output on the SDA line in 2's complement format for bipolar readings and in straight binary for unipolar readings. Input Data Format When the LTC2301/LTC2305 is addressed for a write operation, it acknowledges by pulling SDA low during the low period before the 9th cycle and acts as a receiver. The master/transmitter can then send 1 byte to program the device. The input byte consists of the 6-bit DIN word followed by two bits that are ignored by the ADC and are considered don't cares (X) (see Figure 7b). The input bits are latched on the rising edge of SCL during the write operation.
1 2 3 4 5 6 7 8 9
***
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK BY ADC
B11
B10
B9
B8
B7
B6
B5
B4
***
ACK BY MASTER
MOST SIGNIFICANT DATA BYTE READ 1 BYTE 1 2 3 4 5 6 7 8
ADDRESS FRAME
9
SCL (CONTINUED)
***
CONVERSION INITIATED
SDA (CONTINUED)
***
B3
B2
B1
B0 NAK BY MASTER
STOP BY MASTER
LEAST SIGNIFICANT DATA BYTE READ 1 BYTE
23015 F07a
Figure 7a. Timing Diagram for Reading from the LTC2301/LTC2305
NOTE: S/D BIT IS A DON'T CARE (X) FOR THE LTC2301 1 SCL CONVERSION INITIATED SDA START BY MASTER ADDRESS FRAME A6 A5 A4 A3 A2 A1 A0 R/W ACK BY ADC S/D O/S X X UNI SLP X X ACK BY ADC STOP BY MASTER 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
DIN WORD WRITE 1 BYTE
23015 F07b
Figure 7b. Timing Diagram for Writing to the LTC2301/LTC2305
23015f
17
LTC2301/LTC2305 APPLICATIONS INFORMATION
After power-up, the ADC initiates an internal reset cycle which sets the DIN word to all 0s (S/D=O/S=UNI=SLP=0). A write operation may be performed if the default state of the ADC's configuration is not desired. Otherwise, the ADC must be properly addressed and followed by a Stop condition to initiate a conversion. Initiating a New Conversion The LTC2301/LTC2305 awakens from either nap or sleep when properly addressed for a read/write operation. A Stop command may then be issued after performing the read/write operation to trigger a new conversion. Issuing a Stop command after the 8th SCL clock pulse of the address frame and before the completion of a read/write operation will also initiate new conversion, but the output result may not be valid due to lack of adequate acquisition time (see Acquisition section). LTC2301/LTC2305 Address The LTC2301/LTC2305 have two address pins (AD0 and AD1) that may be tied high, low or left floating to enable one of the 9 possible addresses (see Table 2). In addition to the configurable addresses listed in Table 2, the LTC2301/LTC2305 also contain a global address (1110111) which may be used for synchronizing multiple LTC2301/LTC2305s or other I2C LTC230X SAR ADCs (see Synchronizing Multiple LTC2301/LTC2305s with Global Address Call section).
Table 2. Address Assignment
AD1 LOW LOW LOW FLOAT FLOAT FLOAT HIGH HIGH HIGH AD0 LOW FLOAT HIGH HIGH FLOAT LOW LOW FLOAT HIGH ADDRESS 0001000 0001001 0001010 0001011 0011000 0011001 0011010 0011011 0101000
Continuous Read In applications where the same input channel is sampled each cycle, conversions can be continuously performed and read without a write cycle (see Figure 8). The DIN word remains unchanged from the last value written into the device. If the device has not been written to since powerup, the DIN word defaults to all 0s (S/D=O/S=UNI=SLP=0). At the end of a read operation, a Stop condition may be given to start a new conversion. At the conclusion of the conversion cycle, the next result may be read using the method described above. If the conversion cycle is not concluded and a valid address selects the device, the LTC2301/LTC2305 generates a NAK signal indicating the conversion cycle is in progress.
S
7-BIT ADDRESS
R
ACK
READ
P
S
7-BIT ADDRESS
R
ACK
READ
P
CONVERSION
NAP
DATA OUTPUT
CONVERSION
NAP
DATA OUTPUT
CONVERSION
23015 F08
Figure 8. Consecutive Reading with the Same Configuration
23015f
18
LTC2301/LTC2305 APPLICATIONS INFORMATION
Continuous Read/Write Once the conversion cycle is complete, the LTC2301/ LTC2305 can be written to and then read from using the Repeated Start (Sr) command. Figure 9 shows a cycle which begins with a data Write, a repeated Start, followed by a Read and concluded with a Stop command. The following conversion begins after all 16 bits are read out of the device or after a Stop command. The following conversion will be performed using the newly programmed data. Synchronizing Multiple LTC2301/LTC2305s with a Global Address Call In applications where several LTC2301/LTC2305s or other I2C SAR ADCs from Linear Technology Corporation are used on the same I2C bus, all converters can be synchronized through the use of a global address call. Prior to issuing the global address call, all converters must have completed a conversion cycle. The master then issues a Start, followed by the global address 1110111, and a write request. All converters will be selected and acknowledge the request. The master then sends a write byte (optional) followed by the Stop command. This will update the channel selection (optional) and simultaneously initiate a conversion for all ADCs on the bus (see Figure 10). In order to synchronize multiple converters without changing the channel, a Stop command may be issued after acknowledgement of the global write command. Global read commands are not allowed and the converters will NAK a global read request. Nap Mode The ADCs enter nap mode after a conversion is complete (tCONV) if the SLP bit is set to a logic 0. The supply current decreases to 225A in nap mode between conversions, thereby reducing the average power dissipation as the sample rate decreases. For example, the LTC2301/LTC2305 draw an average of 300A at a 1ksps sampling rate. The LTC2301/LTC2305 keep only the reference (VREF) and reference buffer (REFCOMP) circuitry active when in nap mode.
S
7-BIT ADDRESS
W
ACK
WRITE
Sr
7-BIT ADDRESS
R
ACK
READ
P
CONVERSION
NAP
DATA OUTPUT
CONVERSION
DATA OUTPUT
CONVERSION
23015 F09
Figure 9. Write, Read, Start Conversion
SCL SDA
LTC2301/LTC2305
LTC2301/LTC2305
LTC2301/LTC2305
S
GLOBAL ADDRESS
W
ACK
WRITE (OPTIONAL)
P
CONVERSION
NAP
DATA OUTPUT
CONVERSION OF ALL LTC2301/05s
23015 F10
Figure 10. Synchronize Multiple LTC2301/LTC2305s with a Global Address Call
23015f
19
LTC2301/LTC2305 APPLICATIONS INFORMATION
Sleep Mode The ADCs enter sleep mode after a conversion is complete (tCONV) if the SLP bit is set to a logic 1. The ADCs draw only 7A in sleep mode, provided that none of the digital inputs are switching. When the LTC2301/LTC2305 are properly addressed, the ADCs are released from sleep mode and require 200ms (tREFWAKE) to wake up and charge the respective 2.2F and 10F bypass capacitors on the VREF and REFCOMP pins. A new conversion should not be initiated before this time as shown in Figure 11. Acquisition The LTC2301/LTC2305 begin acquiring the input signal at different instances depending on whether a read or write operation is being performed. If a read operation is being performed, acquisition of the input signal begins on the rising edge of the 9th clock pulse following the address frame as shown in Figure 12a. If a write operation is being performed, acquisition of the input signal begins on the falling edge of the sixth clock cycle after the DIN word has been shifted in as shown in Figure 12b. The LTC2301/LTC2305 will acquire the signal from the input channel that was most recently programmed by the DIN word. A minimum of 240ns is required to acquire the input signal before initiating a new conversion. Board Layout and Bypassing To obtain the best performance, a printed circuit board with a solid ground plane is required. Layout for the printed board should ensure digital and analog signal lines are
S
7-BIT ADDRESS
R/W
ACK
P
CONVERSION
SLEEP
tREFWAKE
CONVERSION
23015 F11
Figure 11. Exiting Sleep Mode and Starting a New Conversion
1 SCL
2
3
4
5
6
7
8
9
1
2
ACQUISITION BEGINS SDA A6 A5 A4 A3 A2 A1 A0 R/W tACQ B11 B10
23015 F12a
Figure 12a. Timing Diagram Showing Acquisition During a Read Operation
5 SCL
6
7
8
9
1
2
3
4
5
6
7
8
9
ACQUISITION BEGINS SDA A2 A1 A0 R/W S/D O/S X X UNI SLP X X tACQ
23015 F12b
Figure 12b. Timing Diagram Showing Acquisition During a Write Operation
23015f
20
LTC2301/LTC2305 APPLICATIONS INFORMATION
separated as much as possible. Care should be taken not to run any digital signals alongside an analog signal. All analog inputs should be shielded by GND. VREF, REFCOMP and VDD should be bypassed to the ground plane as close to the pin as possible. Maintaining a low impedance path for the common return of these bypass capacitors is essential to the low noise operation of the ADC. These traces should be as wide as possible. See Figure 15a-15e for a suggested layout.
OUTPUT CODE (TWO'S COMPLEMENT)
011...111 011...110 000...001 000...000 111...111 111...110 100...001 100...000 -FS/2 FS = 4.096V 1LSB = FS/2n 1LSB = 1mV -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB
23015 F13
111...111 BIPOLAR ZERO OUTPUT CODE 111...110 100...001 100...000 011...111 UNIPOLAR ZERO 011...110 000...001 000...000 0V INPUT VOLTAGE (V) FS = 4.096V 1LSB = FS/2n 1LSB = 1mV FS - 1LSB
23015 F14
Figure 13. Bipolar Transfer Characteristics (2's Complement)
Figure 14. Unipolar Transfer Characteristics (Straight Binary)
Figure 15a. Top Silkscreen
23015f
21
LTC2301/LTC2305 APPLICATIONS INFORMATION
Figure 15b. Topside
Figure 15c. Layer 2 Ground Plane
Figure 15d. Layer 3 Power Plane
Figure 15e. Bottomside
23015f
22
LTC2301/LTC2305 PACKAGE DESCRIPTION
DE/UE Package 12-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1695)
4.00 0.10 (2 SIDES) 0.70 0.05 3.30 0.05 1.70 0.05 PACKAGE OUTLINE 0.25 0.05 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.00 - 0.05 PIN 1 TOP MARK (NOTE 6) R = 0.05 TYP 3.00 0.10 (2 SIDES) 3.30 0.10 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER
(UE12/DE12) DFN 0806 REV D
7
R = 0.115 TYP
0.40 0.10 12
3.60 0.05 2.20 0.05
0.50 BSC
0.200 REF
0.75 0.05
6 0.25 0.05 2.50 REF
1 0.50 BSC
BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
MS Package 12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev O)
0.889 (.035 0.127 .005)
5.23 (.206) MIN
3.20 - 3.45 (.126 - .136)
0.42 0.038 (.0165 .0015) TYP
0.65 (.0256) BSC
4.039 0.102 (.159 .004) (NOTE 3)
12 11 10 9 8 7
RECOMMENDED SOLDER PAD LAYOUT
DETAIL "A" 0 - 6 TYP
0.406 0.076 (.016 .003) REF
0.254 (.010) GAUGE PLANE
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE
1.10 (.043) MAX
123456
0.86 (.034) REF
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.22 - 0.38 (.009 - .015) TYP
0.650 (.0256) BSC
0.1016 (.004
0.0508 .002)
MSOP (MS12) 1107 REV O
23015f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2301/LTC2305 TYPICAL APPLICATION
5V 0.1F IN OUT LT1790-2.5 GND 10V 7 8 50k 450k VDD LTC2305 AD1 AD0 1.7k 1.7k 10F 0.1F
Driving the LTC2305 with 10V Input Signals Using a Precision Attenuator
1F 5V
450k
2 150k 10V INPUT SIGNAL 3 50k 4pF 4 -10V GND
23015 TA02
RELATED PARTS
PART NUMBER LTC1417 LTC1468/LT1469 LTC1609 LTC1790 LTC1850/LTC1851 LTC1852/LTC1853 LTC1860/LTC1861 LTC1863/LTC1867 LTC1864/LTC1865 LTC2302/LTC2306 LTC2308 LTC2309 LTC2451/LTC2453 LTC2487/LTC2489/ LTC2493 LTC2495/LTC2497/ LTC2499 DESCRIPTION 14-Bit, 400ksps Serial ADC 16-Bit, 200ksps Serial ADC Micropower Low Dropout Reference 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC 10-Bit/12-Bit, 8-Channel, 400ksps ADC 12-Bit, 1-/2-Channel 250ksps ADC in MSOP 12-/16-Bit, 8-Channel 200ksps ADC 16-Bit, 1-/2-Channel 250ksps ADC in MSOP 12-Bit, 1-/2-Channel 500ksps SPI ADCs in 3mm x 3mm DFN 12-Bit, 8-Channel 500ksps SPI ADC 12-Bit, 8-Channel ADC with I2C Interface Easy-to-Use, Ultra-Tiny 16-Bit I2C Delta Sigma ADCs 2-/4-Channel Easy Drive I2C Delta Sigma ADCs 8-/16-Channel Easy Drive I2C Delta Sigma ADCs COMMENTS 20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package 65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply 60A Supply Current, 10ppm/C, SOT-23 Package Parallel Output, Programmable MUX and Sequencer, 5V Supply Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package 2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package 850A at 250ksps, 2A at 1ksps, SO-8 and MSOP Packages 450A at 150ksps, 10A at 1ksps, SO-8 and MSOP Packages 14mW at 500ksps, Single 5V Supply, Software Compatible with LTC2308 5V, Internal Reference, 4mm x 4mm QFN Package, Software Compatible with LTC2302/LTC2306 5V, Internal Reference, 4mm x 4mm QFN and 20-Pin TSSOP Packages, Software Compatible with LTC2301/LTC2305 2 LSB INL, 50nA Sleep Current, 60Hz Output Rate, 3mm x 2mm DFN Package, Single-Ended/Differential Inputs 16-/24-Bits, PGA and Temp Sensor, 4mm x 3mm DFN Packages 16-/24-Bits, PGA and Temp Sensor, 5mm x 7mm QFN Packages
23015f
Single/Dual 90MHz, 22V/s, 16-Bit Accurate Op Amps Low Input Offset: 75V/125V
LTC1860L/LTC1861L 3V, 12-Bit, 1-/2-Channel 150ksps ADC LTC1863L/LTC1867L 3V, 12-/16-Bit, 8-Channel 175ksps ADC LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADC in MSOP
24 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008
+
1 450k
-
LT1991
9 150k 10
4pF
6 100 47pF
CH0 CH1
450k
ANALOG INPUT MUX
+ -
SCL
12-BIT SAR ADC
I2C PORT
SDA
CONTROL LOGIC (FPGA, CPLD, DSP ETC) ,
5
INTERNAL 2.5V REF
VREF 2.2F REFCOMP 0.1F 10F
LT 0808 * PRINTED IN USA

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Price & Availability of LTC2301

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